CD74FCT843AM ,BiCMOS FCT Interface Logic 9-Bit Non-Inverting Transparent Latches with 3-State OutputsCD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTSSCBS727 – JULY 2000M PACKAGE ..
CD74HC00 ,High Speed CMOS Logic Quad 2-Input NAND GatesCD54HC00, CD74HC00,CD54HCT00, CD74HCT00Data sheet acquired from Harris SemiconductorSCHS116CHigh-Sp ..
CD74HC00E ,High Speed CMOS Logic Quad 2-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC00EE4 ,High Speed CMOS Logic Quad 2-Input NAND Gates 14-PDIP -55 to 125Maximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC00M ,High Speed CMOS Logic Quad 2-Input NAND GatesFeatures Description• Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, andCD74HCT00 logic gates u ..
CD74HC00M ,High Speed CMOS Logic Quad 2-Input NAND GatesCD54HC00, CD74HC00,CD54HCT00, CD74HCT00Data sheet acquired from Harris SemiconductorSCHS116CHigh-Sp ..
CIUH11D66 , INVERTER
CJ7805 , Three-terminal positive voltage regulator
CJ7808 , Three-terminal positive voltage regulator
CJ7808 , Three-terminal positive voltage regulator
CJ78L06 , THREE TERMINAL POSITIVE VOLTAGE REGULATOR
CJ78L06 , THREE TERMINAL POSITIVE VOLTAGE REGULATOR
CD74FCT843AM
BiCMOS FCT Interface Logic 9-Bit Non-Inverting Transparent Latches with 3-State Outputs
Input/Output Isolation From VCC-
Controlled Output Edge Rates 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Processand Circuit Design Packaged in Plastic Small-Outline Package
descriptionThe CD74FCT843A is a 9-bit, bus-interface,
D-type latch with 3-state outputs, designed
specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS
transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing
(0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC
bounce and ground bounce and their effects during simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking 48 mA.
The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches
are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE) input controls
the 3-state outputs. When OE is high, the outputs are in the high-impedance state. The latch operation is
independent of the state of the output enable. This device, having preset (PRE) and clear (CLR), are ideal for
parity-bus interfacing. When PRE is low, the outputs are high if OE is low. PRE overrides CLR. When CLR is
low, the outputs are low if OE is low. When CLR is high, data can be entered into the latch. The device provides
noninverted outputs.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
The CD74FCT843A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLR
GND
PRE
