CD74ACT280M ,9-Bit Odd/Even Parity Generator/CheckerCD54/74AC280,CD54/74ACT280Data sheet acquired from Harris SemiconductorSCHS250AAugust 1998 - Revise ..
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CD74ACT280E-CD74ACT280M
9-Bit Odd/Even Parity Generator/Checker
CD54/74AC280, CD54/74ACT280 SCHS250A August 1998 - Revised May 2000 9-Bit Odd/Even Parity Generator/Checker data inputs is HIGH. Odd parity is indicated (∑O output is Features HIGH) when an odd number of data inputs is HIGH. Parity • Buffered Inputs checking for words larger than nine bits can be accom- plished by tying the ∑E output to any input of an additional • Typical Propagation Delay ’AC280, ’ACT280 parity checker. o - 10ns at V = 5V, T = 25 C, C = 50pF CC A L • Exceeds 2kV ESD Protection per MIL-STD-883, Ordering Information Method 3015 PART TEMP. • SCR-Latchup-Resistant CMOS Process and Circuit o NUMBER RANGE ( C) PACKAGE Design CD54AC280F3A -55 to 125 14 Ld CERDIP • Speed of Bipolar FAST™/AS/S with Significantly o Reduced Power Consumption CD74AC280E 0 to 70 C, -40 to 85, 14 Ld PDIP -55 to 125 • Balanced Propagation Delays o CD74AC280M 0 to 70 C, -40 to 85, 14 Ld SOIC • AC Types Feature 1.5V to 5.5V Operation and -55 to 125 Balanced Noise Immunity at 30% of the Supply CD54ACT280F3A -55 to 125 14 Ld CERDIP •–24mA Output Drive Current o CD74ACT280E 0 to 70 C, -40 to 85, 14 Ld PDIP - Fanout to 15 FAST™ ICs -55 to 125 o - Drives 50W Transmission Lines CD74ACT280M 0 to 70 C, -40 to 85, 14 Ld SOIC -55 to 125 Description NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to The ’AC280 and ’ACT280 are 9-bit odd/even parity genera- obtain the variant in the tape and reel. tor/checkers that utilize Advanced CMOS Logic technology. 2. Wafer and die for this part number is available which meets all elec- Both even and odd parity outputs are available for checking trical specifications. Please contact your local TI sales office or cus- or generating parity for words up to nine bits long. Even par- tomer service for ordering information. ity is indicated (∑E output is HIGH) when an even number of Pinout Functional Diagram CD54AC280, CD54ACT280 (CERDIP) CD74AC280, CD74ACT280 (PDIP, SOIC) 8 I0 TOP VIEW 9 I1 10 I2 5 I6 1 14 V CC ∑ EVEN 11 I7 2 13 I5 I3 12 NC 3 12 I4 I4 6 ∑ ODD I8 4 11 I3 13 I5 ∑E 5 10 I2 1 I6 ∑O 6 9 I1 2 I7 GND 7 8 I0 GND = 7 4 V = 14 CC I8 NC = 3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Fairchild Semiconductor. 1 Copyright © 2000,
