CD74ACT175M96 ,Quad D-Type Flip-Flops with Resetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74ACT191E , Presettable Synchronous 4-Bit Binary Up/Down Counter
CD74ACT191E , Presettable Synchronous 4-Bit Binary Up/Down Counter
CD74ACT20 ,Dual 4-Input NAND Gates CD54ACT20, CD74ACT20DUAL 4-INPUT POSITIVE-NAND GATESSCHS320 – NOVEMBER 2002CD54ACT20 ...F PACKAGE* ..
CD74ACT20E ,Dual 4-Input NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74ACT20M ,Dual 4-Input NAND Gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL21NR10KNE , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74ACT175E-CD74ACT175M-CD74ACT175M96
Quad D-Type Flip-Flops with Reset
Speed of Bipolar F, AS, and S, WithSignificantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015 Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
description/ordering informationThis positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features
complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
CLK
