CD74ACT174M ,Hex D-Type Flip-Flops with Resetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74ACT174M96 ,Hex D-Type Flip-Flops with Resetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74ACT175E ,Quad D-Type Flip-Flops with Resetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74ACT175E ,Quad D-Type Flip-Flops with Resetfeaturescomplementary outputs from each flip-flop.Information at the data (D) inputs meeting the se ..
CD74ACT175E ,Quad D-Type Flip-Flops with Resetelectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
CD74ACT175M ,Quad D-Type Flip-Flops with Reset CD74ACT175 QUADRUPLE D-TYPE FLIP-FLOPWITH CLEARSCHS345 – APRIL 2003E OR M PACKAGE* Inputs Are TTL- ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74ACT174E-CD74ACT174M-CD74ACT174M96
Hex D-Type Flip-Flops with Reset
Speed of Bipolar F, AS, and S, WithSignificantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015 Applications Include:
– Buffer/Storage Registers
– Shift Registers
description/ordering informationThe ’ACT174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are
designed for 4.5-V to 5.5-V VCC operation.
Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)GND
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
