CD74ACT112M ,Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS323 – J ..
CD74ACT138E ,3-Line to 8-Line Inverting Decoders/Demultiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74ACT138E ,3-Line to 8-Line Inverting Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74ACT138E ,3-Line to 8-Line Inverting Decoders/Demultiplexers CD54ACT138, CD74ACT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS329A – JANUARY 2003 – REVISED ..
CD74ACT138M ,3-Line to 8-Line Inverting Decoders/Demultiplexerselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
CD74ACT138MG4 , 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74ACT112M
Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset
±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop) Output states are unpredictable if PRE and CLR go high
simultaneously after both being low at the same time.
1PRE
GND
2CLR
2CLK
2PRE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
