CD74ACT109E ,Dual Positive-Edge Triggered J-K Flip-Flops with Set and Resetelectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
CD74ACT109E ,Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset/sc/package.FUNCTION TABLE(each flip-flop)INPUTS OUTPUTSPRE CLR CLK J K Q QL H X X X H LH LX X X L ..
CD74ACT109E ,Dual Positive-Edge Triggered J-K Flip-Flops with Set and Resetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74ACT109M ,Dual Positive-Edge Triggered J-K Flip-Flops with Set and Resetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74ACT109M ,Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS327 – J ..
CD74ACT10E ,Triple 3-Input NAND Gates
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74ACT109E-CD74ACT109M
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset
±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop) Unpredictable and unstable condition if both PRE and CLR
go high simultaneously after both being low at the same
time
1CLK
1PRE
GND
2CLK
2PRE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
