CD74AC74M96 ,Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Resetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC74M96G4 ,Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset 14-SOIC -55 to 125maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74AC86E ,Quad 2-Input Exclusive-OR Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC86M ,Quad 2-Input Exclusive-OR Gates CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCHS324 – JANUARY 2003E OR M PACKAGE* AC Types Featu ..
CD74AC86M ,Quad 2-Input Exclusive-OR Gates/sc/package.FUNCTION TABLE(each gate)INPUTSOUTPUTYA BL L LL HHH LHH H LPlease be aware that an impo ..
CD74ACT00 ,Quad 2-Input NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74AC74-CD74AC74E-CD74AC74M-CD74AC74M96-CD74AC74M96G4
Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe ’AC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop) This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1CLK
1PRE
GND
2CLK
2PRE
