CD74AC174M96 ,Hex D-Type Flip-Flops with Resetlogic diagram (positive logic)1CLR9CLK31D1D2C1 1QRTo Five Other Channels†absolute
CD74AC175M96 ,Quad D-Type Flip-Flops with Resetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC20 ,Dual 4-Input NAND Gates SCHS229B – SEPTEMBER 1998 – REVISED NOVEMBER 2002E OR M PACKA ..
CD74AC20E ,Dual 4-Input NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC20M ,Dual 4-Input NAND Gatesmaximum ratings over operating free-air temperature rangeSupply voltage range, V . . . . . . . . . ..
CD74AC20M ,Dual 4-Input NAND Gateslogic diagram (positive logic)1 91A 2A1021B 68 2B1Y 2Y4 121C 2C5 131D 2DPlease be aware that an imp ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74AC174E-CD74AC174M-CD74AC174M96
Hex D-Type Flip-Flops with Reset
Buffered Inputs Speed of Bipolar F, AS, and S, WithSignificantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015 Applications Include:
– Buffer/Storage Registers
– Shift Registers
description/ordering informationThe CD74AC174 is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input and is designed for
1.5-V to 5.5-V VCC operation.
Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)GND
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
