CD74AC139M96 ,Dual 2-to-4 Line Decoder/Demultiplexer CD54AC139, CD74AC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCHS332 – MARCH 2003CD54AC139 . ..
CD74AC14 ,Hex Schmitt-Triggered Inverters SCHS228B − SEPTEMBER 1998 − REVISED MARCH 2004E OR M PACKAGE AC Typ ..
CD74AC14E ,Hex Schmitt-Triggered Invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC14E ,Hex Schmitt-Triggered Inverters/sc/package.FUNCTION TABLE(each inverter)INPUT OUTPUTA YH LL H
CD74AC14E ,Hex Schmitt-Triggered Inverters SCHS228B − SEPTEMBER 1998 − REVISED MARCH 2004E OR M PACKAGE AC Typ ..
CD74AC14M ,Hex Schmitt-Triggered Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74AC139E-CD74AC139M96
Dual 2-to-4 Line Decoder/Demultiplexer
Cascading and/or Data Reception Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe ’AC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 1.5-V to 5.5-V VCC operation.
These devices are designed to be used in high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders can be
used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable
circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical
access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The active-low enable (G) input can be used as a data line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its
driving circuit.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Y0
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
