CD74AC10M96 ,Triple 3-Input NAND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74AC112E ,Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Resetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC112M ,Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Resetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74AC112M96 ,Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS325 – JAN ..
CD74AC112M96G4 ,Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125logic diagram (positive logic)Q QPRE CLRK JCLK†absolute
CD74AC138E ,3-Line to 8-Line Inverting Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD74AC10E-CD74AC10M-CD74AC10M96
Triple 3-Input NAND Gates
Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe CD74AC10 contains three independent 3-input NAND gates. This device performs the Boolean function
Y = A • B • C or Y = A + B + C in positive logic.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
logic diagram, each gate (positive logic)GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
