CD54HCT75F3A ,High Speed CMOS Logic Dual 2-Bit Bistable Transparent LatchMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT85F3A ,High Speed CMOS Logic 4-Bit Magnitude ComparatorMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT86F ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT86F ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT86F3A ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesFeatures Description• Typical Propagation Delay: 9ns at V = 5V, The ’HC86 and ’HCT86 contain four i ..
CD54HCT86F3A ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesCD54HC86, CD74HC86,CD54HCT86, CD74HCT86Data sheet acquired from Harris SemiconductorSCHS137DHigh-Sp ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD54HCT75F3A
High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 SCHS135F Dual 2-Bit Bistable March 1998 - Revised October 2003 Transparent Latch Features Description • True and Complementary Outputs The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by • Buffered Inputs and Outputs [ /Title separate Enable inputs (1E and 2E) which are active LOW. (CD74 When the Enable input is HIGH data enters the latch and • Fanout (Over Temperature Range) appears at the Q output. When the Enable input (1E and 2E) HC75, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads is LOW the output is not affected. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74 o o HCT75 Ordering Information • Wide Operating Temperature Range . . . -55 C to 125 C ) • Balanced Propagation Delay and Transition Times TEMP. RANGE Sub- o / PART NUMBER ( C) PACKAGE • Significant Power Reduction Compared to LSTTL ject CD54HC75F3A -55 to 125 16 Ld CERDIP Logic ICs (Dual CD54HCT75F3A -55 to 125 16 Ld CERDIP • HC Types 2-Bit - 2V to 6V Operation CD74HC75E -55 to 125 16 Ld PDIP Bistabl - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC75M -55 to 125 16 Ld SOIC e at V = 5V CC CD74HC75MT -55 to 125 16 Ld SOIC • HCT Types CD74HC75M96 -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation CD74HC75NSR -55 to 125 16 Ld SOP - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V = 2V (Min) V IL IH CD74HC75PW -55 to 125 16 Ld TSSOP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC75PWR -55 to 125 16 Ld TSSOP CD74HCT75E -55 to 125 16 Ld PDIP CD74HCT75M -55 to 125 16 Ld SOIC CD74HCT75PWT -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC75, CD54HCT75 (CERDIP) CD74HC75 (PDIP, SOIC, SOP, TSSOP) CD74HCT75 (PDIP, SOIC, TSSOP) TOP VIEW 16 1Q0 1Q0 1 1D0 2 15 1Q1 1D1 3 14 1Q1 2E 4 13 1E V 5 12 GND CC 2D0 6 11 2Q0 2D1 7 10 2Q0 2Q1 8 9 2Q1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
