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CD54HCT573FTI,TIN/a500avaiHigh Speed CMOS Logic Octal Transparent Latch with 3-State Output
CD54HCT573F3AHARN/a2avaiHigh Speed CMOS Logic Octal Transparent Latch with 3-State Output


CD54HCT573F ,High Speed CMOS Logic Octal Transparent Latch with 3-State Output/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
CD54HCT573F3A ,High Speed CMOS Logic Octal Transparent Latch with 3-State Outputmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD54HCT574F ,High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State OutputsCD54/74HC374, CD54/74HCT374,CD54/74HC574, CD54/74HCT574Data sheet acquired from Harris Semiconducto ..
CD54HCT574F ,High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State OutputsFeatures Description• Buffered Inputs The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-typeflip ..
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CD54HCT573F-CD54HCT573F3A
High Speed CMOS Logic Octal Transparent Latch with 3-State Output
Standard Outputs Drive Up To 10 LS-TTLLoads Significant Power Reduction Compared to
LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible
description/ordering information

The ’HCT573 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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