CD54HCT390F3A ,High Speed CMOS Logic Dual Decade Ripple CounterFeatures Description• Two BCD Decade or Bi-Quinary Counters The CD74HC390 and ’HCT390 dual 4-bit de ..
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CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
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CD54HCT390F3A
High Speed CMOS Logic Dual Decade Ripple Counter
CD74HC390, CD54HCT390, CD74HCT390 SCHS185C High-Speed CMOS Logic September 1997 - Revised October 2003 Dual Decade Ripple Counter Features Description • Two BCD Decade or Bi-Quinary Counters The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are • One Package Can Be Configured to Divide-by-2, 4, [ /Title pin compatible with low-power Schottky TTL (LSTTL). These 5,10, 20, 25, 50 or 100 (CD74 devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide- • Two Master Reset Inputs to Clear Each Decade HC390 by-5 sections. These sections are normally used in a BCD Counter Individually , decade or bi-quinary configuration, since they share a com- • Fanout (Over Temperature Range) D74 C mon master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the HCT39 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads counter, a number of counting configurations are possible 0) - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads within one package. The separate clock inputs (nCP0 and /Sub- o o • Wide Operating Temperature Range . . . -55 C to 125 C nCP1) of each section allow ripple counter or frequency divi- ject sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. • Balanced Propagation Delay and Transition Times Each section is triggered by the High-to-Low transition of the (High input pulses (nCP0 and nCP1). • Significant Power Reduction Compared to LSTTL Speed Logic ICs For BCD decade operation, the nQ0 output is connected to CMOS the nCP1 input of the divide-by-5 section. For bi-quinary • HC Types decade operation, the nO3 output is connected to the nCP0 - 2V to 6V Operation input and nQ becomes the decade output. 0 - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which oper- • HCT Types ates on the portion of the counter identified by the “1” and “2” - 4.5V to 5.5V Operation prefixes in the pin configuration. A High level on the nMR - Direct LSTTL Input Logic Compatibility, input overrides the clock and sets the four outputs Low. V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V Ordering Information l OL OH TEMP. RANGE o PART NUMBER ( C) PACKAGE Pinout CD54HCT390F3A -55 to 125 16 Ld CERDIP CD54HCT390 (CERDIP) CD74HC390E -55 to 125 16 Ld PDIP CD74HC390, CD74HCT390 (PDIP, SOIC) CD74HC390M -55 to 125 16 Ld SOIC TOP VIEW CD74HC390MT -55 to 125 16 Ld SOIC 1CP0 1 16 V CC CD74HC390M96 -55 to 125 16 Ld SOIC 1MR 2 15 2CP0 CD74HCT390E -55 to 125 16 Ld PDIP 1Q 3 14 2MR 0 1CP1 4 13 2Q0 CD74HCT390M -55 to 125 16 Ld SOIC 1Q 5 12 2CP1 1 CD74HCT390MT -55 to 125 16 Ld SOIC 1Q 6 11 2Q 2 1 CD74HCT390M96 -55 to 125 16 Ld SOIC 1Q 7 10 2Q 3 2 GND 8 9 2Q 3 NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
