CD54HCT373F3A ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD54HCT374F3A ,High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State OutputMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT377F3A ,High Speed CMOS Logic Octal D-Type Flip-Flops with Data EnableMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT390F3A ,High Speed CMOS Logic Dual Decade Ripple CounterFeatures Description• Two BCD Decade or Bi-Quinary Counters The CD74HC390 and ’HCT390 dual 4-bit de ..
CD54HCT390F3A ,High Speed CMOS Logic Dual Decade Ripple CounterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT393F ,High Speed CMOS Logic Dual 4-Stage Binary CounterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CIH10T6N8JNC , Chip Inductor; CIH Series
CIH10T6N8JNC , Chip Inductor; CIH Series
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10NR10KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CIL10Y100KNC , It has ferrite and 100% Ag as internal conductors, the CIL Series has excellent Q characteristics and eliminate crosstalk.
CD54HCT373F-CD54HCT373F3A
High Speed CMOS Logic Octal Transparent Latches with 3-State Output
Standard Outputs Drive Up To 10 LS-TTLLoads Significant Power Reduction Compared to
LS-TTL Logic ICs Inputs Are TTL-Voltage Compatible
description/ordering informationThe ’HCT373 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
