CD54HCT175F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with ResetFeaturesLSTTL devices.• Common Clock and Asynchronous Reset on FourInformation at the D input is tr ..
CD54HCT175F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with ResetCD54HC175, CD74HC175,CD54HCT175, CD74HCT175Data sheet acquired from Harris SemiconductorSCHS160CHig ..
CD54HCT175F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with ResetLogic DiagramCCL L ONE OF FOUR F/F4 (5, 12, 13) D3( 6, 11, 14)p pDnQn nnCC LLCC LLppnnC CL LCC 2( 7 ..
CD54HCT175F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD54HCT191F3A ,High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counter ..
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CD54HCT175F3A
High Speed CMOS Logic Quad D-Type Flip-Flops with Reset
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 SCHS160C High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset August 1997 - Revised October 2003 advantage of standard CMOS ICs and the ability to drive 10 Features LSTTL devices. • Common Clock and Asynchronous Reset on Four Information at the D input is transferred to the Q, Q outputs on D-Type Flip-Flops [ /Title the positive going edge of the clock pulse. All four Flip-Flops • Positive Edge Pulse Triggering are controlled by a common clock (CP) and a common reset (CD74 (MR). Resetting is accomplished by a low voltage level • Complementary Outputs HC175 independent of the clock. All four Q outputs are reset to a , • Buffered Inputs logic 0 and all four Q outputs to a logic 1. D74 C • Fanout (Over Temperature Range) Ordering Information HCT17 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads 5) - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE o o o /Sub- PART NUMBER ( C) PACKAGE • Wide Operating Temperature Range . . . -55 C to 125 C ject • Balanced Propagation Delay and Transition Times CD54HC175F3A -55 to 125 16 Ld CERDIP (High • Significant Power Reduction Compared to LSTTL CD54HCT175F3A -55 to 125 16 Ld CERDIP Speed Logic ICs CD74HC175E -55 to 125 16 Ld PDIP CMOS • HC Types Logic - 2V to 6V Operation CD74HC175M -55 to 125 16 Ld SOIC Quad - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC175MT -55 to 125 16 Ld SOIC at V = 5V CC D- CD74HC175M96 -55 to 125 16 Ld SOIC • HCT Types Type - 4.5V to 5.5V Operation Flip- CD74HCT175E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) CD74HCT175M -55 to 125 16 Ld SOIC IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT175MT -55 to 125 16 Ld SOIC Description CD74HCT175M96 -55 to 125 16 Ld SOIC The ’HC175 and ’HCT175 are high speed Quad D-type Flip- NOTE: When ordering, use the entire part number. The suffix 96 Flops with individual D-inputs and Q, Q complementary denotes tape and reel. The suffix T denotes a small-quantity reel of 250. outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption Pinout CD54HC175, CD54HCT175 (CERDIP) CD74HC175, CD74HCT175 (PDIP, SOIC) TOP VIEW MR 1 16 V CC Q 2 15 Q 0 3 Q 3 14 Q 0 3 D 4 13 D 0 3 D 5 12 D 1 2 Q 6 11 Q 1 2 Q 7 10 Q 1 2 GND 8 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
