CD54HCT11F. ,High Speed CMOS Logic Triple 3-Input AND GatesFeatures Description• Buffered Inputs The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOStec ..
CD54HCT11F3A ,High Speed CMOS Logic Triple 3-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT11F3A. ,High Speed CMOS Logic Triple 3-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT123F3A ,High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with ResetsMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT125F3A ,High Speed CMOS Logic Quad Buffer, Three-StateMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT125F3A. ,High Speed CMOS Logic Quad Buffer, Three-StateFeatures Description• Three-State Outputs The ’HC125 and ’HCT125 contain 4 independent three-stateb ..
CHPZ27VPT , SILICON PLANAR POWER ZENER DIODES
CHPZ6V2PT , SILICON PLANAR POWER ZENER DIODES
CHS-01TA , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-01TA1 , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-02TB , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-04MB , SURFACE MOUNT TYPE SLIDE SWITCHES
CD54HCT11F.-CD54HCT11F3A-CD54HCT11F3A.
High Speed CMOS Logic Triple 3-Input AND Gates
CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 SCHS273E High-Speed CMOS Logic August 1997 - Revised September 2003 Triple 3-Input AND Gate Features Description • Buffered Inputs The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL = 5V, • Typical Propagation Delay: 8ns at V [ /Title CC gates with the low power consumption of standard CMOS o C = 15pF, T = 25 C L A (CD54 integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin • Fanout (Over Temperature Range) HCT11 compatible with the standard LS logic family. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads , - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads D74 C Ordering Information o o • Wide Operating Temperature Range . . . -55 C to 125 C HC11, TEMP. RANGE CD74 • Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE HCT11 • Significant Power Reduction Compared to LSTTL CD54HC11F3A -55 to 125 14 Ld CERDIP ) Logic ICs Sub- / CD54HCT11F3A -55 to 125 14 Ld CERDIP • HC Types ject - 2V to 6V Operation CD74HC11E -55 to 125 14 Ld PDIP (High - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC11M -55 to 125 14 Ld SOIC at V = 5V CC CD74HC11MT -55 to 125 14 Ld SOIC • HCT Types - 4.5V to 5.5V Operation CD74HC11M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT11E -55 to 125 14 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT11M -55 to 125 14 Ld SOIC l OL OH CD74HCT11MT -55 to 125 14 Ld SOIC CD74HCT11M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC11, CD54HCT11 (CERDIP) CD74HC11, CD74HCT11 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
