CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC112 and ’HCT112 utilize ..
CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerCD54HC112, CD74HC112,CD54HCT112, CD74HCT112Data sheet acquired from Harris SemiconductorDual J-K Fl ..
CD54HCT11F. ,High Speed CMOS Logic Triple 3-Input AND GatesFeatures Description• Buffered Inputs The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOStec ..
CD54HCT11F3A ,High Speed CMOS Logic Triple 3-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT11F3A. ,High Speed CMOS Logic Triple 3-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD54HCT112F3A
High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Dual J-K Flip-Flop with Set and Reset SCHS141H Negative-Edge Trigger March 1998 - Revised October 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise The ’HC112 and ’HCT112 utilize silicon-gate CMOS Immunity and Increased Input Rise and Fall Times technology to achieve operating speeds equivalent to LSTTL [ /Title parts. They exhibit the low power consumption of standard • Asynchronous Set and Reset (CD74 CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. • Complementary Outputs HC112 , These flip-flops have independent J, K, Set, Reset, and • Buffered Inputs Clock inputs and Q and Q outputs. They change state on the D74 C = 60MHz at V = 5V, C = 15pF, • Typical f MAX CC L negative-going transition of the clock pulse. Set and Reset o HCT11 T = 25 C A are accomplished asynchronously by low-level inputs. 2) • Fanout (Over Temperature Range) The HCT logic family is functionally as well as pin- /Sub- - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads compatible with the standard LS logic family. ject - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads . (Dual o o • Wide Operating Temperature Range . . . -55 C to 125 C Ordering Information J-K • Balanced Propagation Delay and Transition Times Flip- TEMP. RANGE o PART NUMBER ( C) PACKAGE • Significant Power Reduction Compared to LSTTL Flop Logic ICs CD54HC112F3A -55 to 125 16 Ld CERDIP with • HC Types Set and CD54HCT112F3A -55 to 125 16 Ld CERDIP - 2V to 6V Operation Reset CD74HC112E -55 to 125 16 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC Nega- CD74HC112MT -55 to 125 16 Ld SOIC at V = 5V CC CD74HC112M96 -55 to 125 16 Ld SOIC • HCT Types CD74HC112NSR -55 to 125 16 Ld SOP - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD74HC112PW -55 to 125 16 Ld TSSOP = 0.8V (Max), V = 2V (Min) V IL IH CD74HC112PWR -55 to 125 16 Ld TSSOP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC112PWT -55 to 125 16 Ld TSSOP CD74HCT112E -55 to 125 16 Ld PDIP Pinout NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity CD54HC112, CD54HCT112 (CERDIP) reel of 250. CD74HC112 (PDIP, SOIC, SOP, TSSOP) CD74HCT112 (PDIP) TOP VIEW 1CP 1 16 V CC 1K 2 15 1R 1J 3 14 2R 1S 4 13 2CP 1Q 5 12 2K 1Q 6 11 2J 2Q 7 10 2S GND 8 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
