CD54HCT08F ,High Speed CMOS Logic Quad 2-Input AND GatesFeatures Description• Buffered Inputs The CD54HC08, CD54HCT08, CD74HC08, andCD74HCT08 logic gates u ..
CD54HCT08F3A ,High Speed CMOS Logic Quad 2-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT109F3A ,High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT10F3A ,High Speed CMOS Logic Triple 3-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC112 and ’HCT112 utilize ..
CHPZ27VPT , SILICON PLANAR POWER ZENER DIODES
CHPZ6V2PT , SILICON PLANAR POWER ZENER DIODES
CHS-01TA , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-01TA1 , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-02TB , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-04MB , SURFACE MOUNT TYPE SLIDE SWITCHES
CD54HCT08F-CD54HCT08F3A
High Speed CMOS Logic Quad 2-Input AND Gates
CD54HC08, CD74HC08, CD54HCT08, CD74HCT08 SCHS118C High-Speed CMOS Logic Quad 2-Input AND Gate August 1997 - Revised July 2004 Features Description • Buffered Inputs The CD54HC08, CD54HCT08, CD74HC08, and CD74HCT08 logic gates utilize silicon gate CMOS = 5V, • Typical Propagation Delay: 7ns at V [ /Title CC technology to achieve operating speeds similar to LSTTL o C = 15pF, T = 25 C L A (CD54H gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 • Fanout (Over Temperature Range) C08, LSTTL loads. The 74HCT logic family is functionally pin - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD54H compatible with the standard 74LS logic family. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CT08, o o • Wide Operating Temperature Range . . . -55 C to 125 C CD74H Ordering Information C08, • Balanced Propagation Delay and Transition Times TEMP. RANGE CD74H o PART NUMBER ( C) PACKAGE • Significant Power Reduction Compared to LSTTL CT08) Logic ICs CD54HC08F3A -55 to 125 14 Ld CERDIP /Sub- • HC Types CD54HCT08F3A -55 to 125 14 Ld CERDIP ject - 2V to 6V Operation (High CD74HC08E -55 to 125 14 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC CD74HC08M -55 to 125 14 Ld SOIC • HCT Types CD74HC08MT -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation CD74HC08M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HC08PW -55 to 125 14 Ld TSSOP ≤ 1µA at V , V • CMOS Input Compatibility, I l OL OH CD74HC08PWR -55 to 125 14 Ld TSSOP CD74HCT08E -55 to 125 14 Ld PDIP CD74HCT08M -55 to 125 14 Ld SOIC CD74HCT08MT -55 to 125 14 Ld SOIC CD74HCT08M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, 1
