CD54HC86F3A ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HC86F3A. ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesCD54HC86, CD74HC86,CD54HCT86, CD74HCT86Data sheet acquired from Harris SemiconductorSCHS137DHigh-Sp ..
CD54HCT00 ,High Speed CMOS Logic Quad 2-Input NAND GatesFeatures Description• Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, andCD74HCT00 logic gates u ..
CD54HCT00F ,High Speed CMOS Logic Quad 2-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT00F. ,High Speed CMOS Logic Quad 2-Input NAND GatesCD54HC00, CD74HC00,CD54HCT00, CD74HCT00Data sheet acquired from Harris SemiconductorSCHS116CHigh-Sp ..
CD54HCT00F3A ,High Speed CMOS Logic Quad 2-Input NAND GatesFeatures Description• Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, andCD74HCT00 logic gates u ..
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CD54HC86F3A-CD54HC86F3A.
High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR Gates
CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 SCHS137D High-Speed CMOS Logic August 1997 - Revised September 2003 Quad 2-Input EXCLUSIVE-OR Gate Features Description • Typical Propagation Delay: 9ns at V = 5V, The ’HC86 and ’HCT86 contain four independent CC o C = 15pF, T = 25 C EXCLUSIVE OR gates in one package. They provide the L A [ /Title system designer with a means for implementation of the • Fanout (Over Temperature Range) (CD74 EXCLUSIVE OR function. Logic gates utilize silicon gate - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CMOS technology to achieve operating speeds similar to HC86, - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads LSTTL gates with the low power consumption of standard CD74 o o CMOS integrated circuits. All devices have the ability to drive • Wide Operating Temperature Range . . . -55 C to 125 C HCT86 10 LSTTL loads. The HCT logic family is functionally pin • Balanced Propagation Delay and Transition Times compatible with the standard LS logic family. ) • Significant Power Reduction Compared to LSTTL Sub- / Logic ICs Ordering Information ject • HC Types (High TEMP. RANGE - 2V to 6V Operation o PART NUMBER ( C) PACKAGE Speed - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CMOS at V = 5V CD54HC86F3A -55 to 125 14 Ld CERDIP CC Logic • HCT Types CD54HCT86F3A -55 to 125 14 Ld CERDIP Quad - 4.5V to 5.5V Operation CD74HC86E -55 to 125 14 Ld PDIP - Direct LSTTL Input Logic Compatibility, 2-Input V = 0.8V (Max), V = 2V (Min) IL IH EXCL CD74HC86M -55 to 125 14 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH USIVE CD74HC86MT -55 to 125 14 Ld SOIC OR Applications CD74HC86M96 -55 to 125 14 Ld SOIC • Logical Comparators CD74HCT86E -55 to 125 14 Ld PDIP • Parity Generators and Checkers CD74HCT86M -55 to 125 14 Ld SOIC • Adders and Subtractors CD74HCT86MT -55 to 125 14 Ld SOIC CD74HCT86M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC86, CD54HCT86 (CERDIP) CD74HC86, CD74HCT86 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
