CD54HC646F3A ,High Speed CMOS Logic Octal Inverting Bus Transceiver with 3-State Outputs
CD54HC688F3A ,High Speed CMOS Logic 8-Bit Magnitude ComparatorMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HC688F3A. ,High Speed CMOS Logic 8-Bit Magnitude ComparatorCD54HC688, CD74HC688,CD54HCT688, CD74HCT688Data sheet acquired from Harris SemiconductorSCHS196CHig ..
CD54HC7266F3A ,High Speed CMOS LogicMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HC73F ,High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HC73F ,High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with ResetLogic Diagram14 (7)J12 (9)QJ3(10)K KCL1 (5)13 (8)CP nA QCLR2 (6)R2CD54HC73, CD74HC73, CD74HCT73Abso ..
CHN202UPT , SWITCHING DIODE
CHN202UPT , SWITCHING DIODE
CHN222PT , SWITCHING DIODE
CHP0230-PM , 824 to 849 MHz 28.5 dBm, Cellular InGaP HBT Amplifier Module
CHPZ27VPT , SILICON PLANAR POWER ZENER DIODES
CHPZ6V2PT , SILICON PLANAR POWER ZENER DIODES
CD54HC646F3A
High Speed CMOS Logic Octal Inverting Bus Transceiver with 3-State Outputs
Balanced Propagation Delays andTransition Times Standard Outputs Drive Up To 15 LS-TTL
Loads Significant Power Reduction Compared to
LS-TTL Logic ICs Inputs Are TTL-Voltage Compatible
(CD74HCT646) Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths
description/ordering informationThe CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops,
and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal
registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can
be performed with these devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be
stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one
of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIR
GND
SBA
