CD54HC4046AF ,High Speed CMOS Logic Phase-Locked-Loop with VCOFeatures Description• Operating Frequency Range The ’HC4046A and ’HCT4046A are high-speed silicon-g ..
CD54HC4046AF3A ,High Speed CMOS Logic Phase-Locked-Loop with VCOGeneral DescriptionVCO Phase ComparatorsThe signal input (SIG ) can be directly coupled to the self ..
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CD54HC4049F3A ,High Speed CMOS Logic Hex Inverting BuffersCD54HC4049, CD74HC4049,CD54HC4050, CD74HC4050Data sheet acquired from Harris SemiconductorSCHS205IH ..
CD54HC4049F3A ,High Speed CMOS Logic Hex Inverting BuffersFeatures Description• Typical Propagation Delay: 6ns at V = 5V,CCThe ’HC4049 and ’HC4050 are fabric ..
CD54HC4050F3A ,High Speed CMOS Logic Hex Non-Inverting BuffersLogic DiagramsHC4049 HC4050AYA Y2CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050Absolute
CHF2010CNP500LX , Series 10 W Power RF Chip Termination/Resistor
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CD54HC4046AF-CD54HC4046AF3A
High Speed CMOS Logic Phase-Locked-Loop with VCO
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A SCHS204J High-Speed CMOS Logic February 1998 - Revised December 2003 Phase-Locked Loop with VCO Features Description • Operating Frequency Range The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of - Up to 18MHz (Typ) at V = 5V CC [ /Title the “4000B” series. They are specified in compliance with - Minimum Center Frequency of 12MHz at V = 4.5V CC (CD74 JEDEC standard number 7. • Choice of Three Phase Comparators HC404 The ’HC4046A and ’HCT4046A are phase-locked-loop - EXCLUSIVE-OR circuits that contain a linear voltage-controlled oscillator 6A, - Edge-Triggered JK Flip-Flop (VCO) and three different phase comparators (PC1, PC2 and CD74 PC3). A signal input and a comparator input are common to - Edge-Triggered RS Flip-Flop HCT40 each comparator. • Excellent VCO Frequency Linearity 46A) The signal input can be directly coupled to large voltage • VCO-Inhibit Control for ON/OFF Keying and for Low /Sub- signals, or indirectly coupled (with a series capacitor) to small Standby Power Consumption voltage signals. A self-bias input circuit keeps small voltage ject signals within the linear region of the input amplifiers. With a • Minimal Frequency Drift (High- passive low-pass filter, the 4046A forms a second-order loop Speed • Operating Power Supply Voltage Range PLL. The excellent VCO linearity is achieved by the use of CMOS linear op-amp techniques. - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V - Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V Ordering Information • Fanout (Over Temperature Range) TEMP. RANGE - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads o PART NUMBER ( C) PACKAGE - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD54HC4046AF3A -55 to 125 16 Ld CERDIP o o • Wide Operating Temperature Range . . . -55 C to 125 C CD54HCT4046AF3A -55 to 125 16 Ld CERDIP • Balanced Propagation Delay and Transition Times CD74HC4046AE -55 to 125 16 Ld PDIP CD74HC4046AM -55 to 125 16 Ld SOIC • Significant Power Reduction Compared to LSTTL Logic ICs CD74HC4046AMT -55 to 125 16 Ld SOIC CD74HC4046AM96 -55 to 125 16 Ld SOIC • HC Types CD74HC4046ANSR -55 to 125 16 Ld SOP - 2V to 6V Operation - High Noise Immunity: N = 30%, N = 30% of V CD74HC4046APWR -55 to 125 16 Ld TSSOP IL IH CC at V = 5V CC CD74HC4046APWT -55 to 125 16 Ld TSSOP CD74HCT4046AE -55 to 125 16 Ld PDIP • HCT Types - 4.5V to 5.5V Operation CD74HCT4046AM -55 to 125 16 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT4046AMT -55 to 125 16 Ld SOIC V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT4046AM96 -55 to 125 16 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at VOL, VOH l NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity Applications reel of 250. • FM Modulation and Demodulation • Frequency Synthesis and Multiplication • Frequency Discrimination • Tone Decoding • Data Synchronization and Conditioning • Voltage-to-Frequency Conversion • Motor-Speed Control CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
