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CD54HC4017F3A
High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
Positive-Edge Clocking Balanced Propagation Delay and TransitionTimes High Noise Immunity: NIL = 30%, NIH = 30%
of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and
Also Available in Chip Form (H)
descriptionThe CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each
decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input.
Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output
transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE)
input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when
taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE If n < 5, TC = H; otherwise, TC = L.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
