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CD54HC40103F3A
High Speed CMOS Logic 8-Stage Synchronous Down Counters
CD54HC40103, CD74HC40103, CD74HCT40103 SCHS221D High-Speed CMOS Logic November 1997 - Revised October 2003 8-Stage Synchronous Down Counters Features Description • Synchronous or Asynchronous Preset The ’HC40103 and CD74HCT40103 are manufactured with high speed silicon gate technology and consist of an 8-stage • Cascadable in Synchronous or Ripple Mode [ /Title synchronous down counter with a single output which is (CD74H active when the internal count is zero. The 40103 contains a • Fanout (Over Temperature Range) single 8-bit binary counter. Each has control inputs for C40103, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads enabling or disabling the clock, for clearing the counter to its - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74H maximum count, and for presetting the counter either o o CT4010 • Wide Operating Temperature Range . . . -55 C to 125 C synchronously or asynchronously. All control inputs and the TC output are active-low logic. 3) • Balanced Propagation Delay and Transition Times /Sub- In normal operation, the counter is decremented by one • Significant Power Reduction Compared to LSTTL count on each positive transition of the CLOCK (CP). ject Logic ICs Counting is inhibited when the TE input is high. The TC (High output goes low when the count reaches zero if the TE input • HC Types Speed is low, and remains low for one full clock period. - 2V to 6V Operation CMOS - High Noise Immunity: N = 30%, N = 30% of V When the PE input is low, data at the P0-P7 inputs are IL IH CC Logic 8- at V = 5V clocked into the counter on the next positive clock transition CC regardless of the state of the TE input. When the PL input is • HCT Types low, data at the P0-P7 inputs are asynchronously forced into - 4.5V to 5.5V Operation the counter regardless of the state of the PE, TE, or CLOCK - Direct LSTTL Input Logic Compatibility, inputs. Input P0-P7 represent a single 8-bit binary word for = 0.8V (Max), V = 2V (Min) V the 40103. When the MR input is low, the counter is IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V asynchronously cleared to its maximum count of 255 , l OL OH 10 regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth Ordering Information table. TEMP. RANGE o If all control inputs except TE are high at the time of zero PART NUMBER ( C) PACKAGE count, the counters will jump to the maximum count, giving a CD54HC40103F3A -55 to 125 16 Ld CERDIP counting sequence of 100 or 256 clock pulses long. 16 10 CD74HC40103E -55 to 125 16 Ld PDIP TE input and the TC The 40103 may be cascaded using the output, in either a synchronous or ripple mode. These CD74HC40103M -55 to 125 16 Ld SOIC circuits possess the low power consumption usually CD74HC40103MT -55 to 125 16 Ld SOIC associated with CMOS circuitry, yet have speeds CD74HC40103M96 -55 to 125 16 Ld SOIC comparable to low power Schottky TTL circuits and can drive up to 10 LSTTL loads. CD74HCT40103E -55 to 125 16 Ld PDIP CD74HCT40103M -55 to 125 16 Ld SOIC CD74HCT40103MT -55 to 125 16 Ld SOIC CD74HCT40103M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
