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CD54HC393F3A
High Speed CMOS Logic Dual 4-Stage Binary Counter
CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 SCHS186E High-Speed CMOS Logic September 1997 - Revised August 2003 Dual 4-Stage Binary Counter Features Description • Fully Static Operation The ’HC393 and ’HCT393 are 4-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The • Buffered Inputs [ /Title state of the stage advances one count on the negative (CD74 transition of each clock pulse; a high voltage level on the MR • Common Reset line resets all counters to their zero state. All inputs and HC393 • Negative-Edge Clocking outputs are buffered. , • Fanout (Over Temperature Range) D74 C Ordering Information - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HCT39 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE 3) o PART NUMBER ( C) PACKAGE o o C to 125 C • Wide Operating Temperature Range . . . -55 /Sub- CD54HC393F3A -55 to 125 14 Ld CERDIP ject • Balanced Propagation Delay and Transition Times (High CD54HCT393F3A -55 to 125 14 Ld CERDIP • Significant Power Reduction Compared to LSTTL Speed Logic ICs CD74HC393E -55 to 125 14 Ld PDIP CMOS • HC Types CD74HC393M -55 to 125 14 Ld SOIC - 2V to 6V Operation CD74HC393MT -55 to 125 14 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC CD74HC393M96 -55 to 125 14 Ld SOIC • HCT Types CD74HCT393E -55 to 125 14 Ld PDIP - 4.5V to 5.5V Operation CD74HCT393M -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT393MT -55 to 125 14 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT393M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC393, CD54HCT393 (CERDIP) CD74HC393, CD74HCT393 (PDIP, SOIC) TOP VIEW 1CP 1 14 V CC 1MR 2 13 2CP 1Q0 3 12 2MR 1Q1 4 11 2Q0 1Q2 5 10 2Q1 1Q3 6 9 2Q2 GND 7 8 2Q3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
