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CD54HC377F3ATIN/a500avaiHigh Speed CMOS Logic Octal D-Type Flip-Flops with Data Enable
CD54HC377F3ATI,TIN/a500avaiHigh Speed CMOS Logic Octal D-Type Flip-Flops with Data Enable


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CD54HC377F3A
High Speed CMOS Logic Octal D-Type Flip-Flops with Data Enable
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 SCHS184C High-Speed CMOS Logic September 1997 - Revised February 2004 Octal D-Type Flip-Flop With Data Enable Features Description • Buffered Common Clock The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip- • Buffered Inputs [ /Title flops are loaded simultaneously on the positive edge of the (CD74 clock (CP) when the Data Enable (E) is Low. = 15pF, • Typical Propagation Delay at C L o V = 5V, T = 25 C HC377 CC A Ordering Information , - 14 ns (HC Types D74 - 16 ns (HCT Types) C TEMP. RANGE o PART NUMBER ( C) PACKAGE HCT37 • Fanout (Over Temperature Range) 7) CD54HC377F3A -55 to 125 20 Ld CERDIP - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads /Sub- - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD54HCT377F3A -55 to 125 20 Ld CERDIP ject o o • Wide Operating Temperature Range . . . -55 C to 125 C CD74HC377E -55 to 125 20 Ld PDIP (High • Balanced Propagation Delay and Transition Times Speed CD74HC377M -55 to 125 20 Ld SOIC CMOS • Significant Power Reduction Compared to LSTTL CD74HC377M96 -55 to 125 20 Ld SOIC Logic ICs Logic CD74HC377PW -55 to 125 20 Ld TSSOP Octal • HC Types - 2V to 6V Operation CD74HC377PWR -55 to 125 20 Ld TSSOP D- - High Noise Immunity: N = 30%, N = 30%of V at Type IL IH CC CD74HCT377E -55 to 125 20 Ld PDIP V = 5V CC Flip- CD74HCT377M -55 to 125 20 Ld SOIC • HCT Types - 4.5V to 5.5V Operation CD74HCT377M96 -55 to 125 20 Ld SOIC - Direct LSTTL Input Logic Compatibility, NOTE: When ordering, use the entire part number. The suffixes V = 0.8V (Max), V = 2V (Min) IL IH 96 and R denote tape and reel. - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH Pinout CD54HC377, CD54HCT377 (CERDIP) CD74HC377 (PDIP, SOIC, TSSOP) CD74HCT377 (PDIP, SOIC) TOP VIEW E 1 20 V CC Q 2 19 Q 0 7 D 3 18 D 0 7 D D 4 17 1 6 Q 5 16 Q 1 6 Q 6 15 Q 2 5 D 14 D 7 2 5 D 8 13 D 3 4 Q 9 12 Q 3 4 GND 10 11 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, 1
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