CD54HC373F ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD54HC373F3A ,OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTSmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD54HC374F3A ,High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State OutputFeatures Description• Buffered Inputs The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-typeflip ..
CD54HC374F3A ,High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State OutputFeatures Description• Buffered Inputs The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-typeflip ..
CD54HC374F3A ,High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State OutputMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HC377F3A ,High Speed CMOS Logic Octal D-Type Flip-Flops with Data EnableFeatures Description• Buffered Common Clock The ’HC377 and ’HCT377 are octal D-type flip-flops with a ..
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CD54HC373F-CD54HC373F3A
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Standard Outputs Drive up to 15 LS-TTLLoads Significant Power Reduction Compared to
LS-TTL Logic ICs
description/ordering informationThe ’HC373 devices are octal transparent D-type
latches designed for 2-V to 6-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
