CD54HC27F3A ,High Speed CMOS Logic Triple 3-Input NOR GatesFeatures Description• Buffered Inputs The ’HC27 and ’HCT27 logic gates utilize silicon gate CMOStec ..
CD54HC27F3A ,High Speed CMOS Logic Triple 3-Input NOR GatesCD54HC27, CD74HC27,CD54HCT27, CD74HCT27Data sheet acquired from Harris SemiconductorSCHS132CHigh-Sp ..
CD54HC27F3A ,High Speed CMOS Logic Triple 3-Input NOR GatesFeatures Description• Buffered Inputs The ’HC27 and ’HCT27 logic gates utilize silicon gate CMOStec ..
CD54HC27F3A ,High Speed CMOS Logic Triple 3-Input NOR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD54HC27F3A
High Speed CMOS Logic Triple 3-Input NOR Gates
CD54HC27, CD74HC27, CD54HCT27, CD74HCT27 SCHS132C High-Speed CMOS Logic Triple 3-Input NOR Gate August 1997 - Revised September 2003 Features Description • Buffered Inputs The ’HC27 and ’HCT27 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL = 5V, • Typical Propagation Delay: 7ns at V [ /Title CC gates with the low power consumption of standard CMOS o C = 15pF, T = 25 C L A (CD74 integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin • Fanout (Over Temperature Range) HC27, compatible with the standard LS logic family. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads HCT27 Ordering Information o o • Wide Operating Temperature Range . . . -55 C to 125 C ) TEMP. RANGE Sub- / • Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE ject • Significant Power Reduction Compared to LSTTL CD54HC27F3A -55 to 125 14 Ld CERDIP (High Logic ICs Speed CD54HCT27F3A -55 to 125 14 Ld CERDIP • HC Types CMOS - 2V to 6V Operation CD74HC27E -55 to 125 14 Ld PDIP Logic - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC27M -55 to 125 14 Ld SOIC at V = 5V CC CD74HC27MT -55 to 125 14 Ld SOIC • HCT Types - 4.5V to 5.5V Operation CD74HC27M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT27E -55 to 125 14 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT27M -55 to 125 14 Ld SOIC l OL OH CD74HCT27MT -55 to 125 14 Ld SOIC CD74HCT27M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC27, CD54HCT27 (CERDIP) CD74HC27, CD74HCT27 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
