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CD54HC257F3A
High Speed CMOS Logic Non-Inverting Quad 2-Input Multiplexer with 3-State Outputs
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 SCHS171D High-Speed CMOS Logic Quad 2-Input November 1997 - Revised October 2003 Multiplexer with Three-State Non-Inverting Outputs all other input conditions. Features Moving data from two groups of registers to four common • Buffered Inputs output buses is a common use of the 257. The state of the • Typical Propagation Delay ( In to Output ) = 12ns at [ /Title Select input determines the particular register from which o V = 5V, C = 15pF, T = 25 C the data comes. It can also be used as a function generator. CC L A (CD74 • Fanout (Over Temperature Range) HC257 Ordering Information , - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads D74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE C o PART NUMBER ( C) PACKAGE o o HCT25 C to 125 C • Wide Operating Temperature Range . . . -55 7) CD54HC257F3A -55 to 125 16 Ld CERDIP • Balanced Propagation Delay and Transition Times /Sub- • Significant Power Reduction Compared to LSTTL CD54HCT257F3A -55 to 125 16 Ld CERDIP Logic ICs ject CD74HC257E -55 to 125 16 Ld PDIP • HC Types (High - 2V to 6V Operation CD74HC257M -55 to 125 16 Ld SOIC Speed = 30%, N = 30% of V - High Noise Immunity: N IL IH CC CMOS at V = 5V CD74HC257MT -55 to 125 16 Ld SOIC CC Logic • HCT Types CD74HC257M96 -55 to 125 16 Ld SOIC Quad - 4.5V to 5.5V Operation CD74HCT257E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, 2-Input V = 0.8V (Max), V = 2V (Min) IL IH Multi- CD74HCT257M -55 to 125 16 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH plexer CD74HCT257MT -55 to 125 16 Ld SOIC Description CD74HCT257M96 -55 to 125 16 Ld SOIC The ’HC257 and ’HCT257 are quad 2-input multiplexers NOTE: When ordering, use the entire part number. The suffix 96 which select four bits of data from two sources under the denotes tape and reel. The suffix T denotes a small-quantity reel of control of a common Select Input (S). The Output Enable 250. input (OE) is active LOW. When OE is HIGH, all of the out- puts (1Y-4Y) are in the high impedance state regardless of Pinout CD54HC257, CD54HCT257 (CERDIP) CD74HC257, CD74HCT257 (PDIP, SOIC) TOP VIEW S 1 16 V CC 1I 2 15 OE 0 1I 3 14 4I 1 0 1Y 4 13 4I 1 2I 5 12 4Y 0 2I 6 11 3I 1 0 10 3I 2Y 7 1 9 3Y GND 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
