CD54HC21F3A ,High Speed CMOS Logic Dual 4-Input AND GatesFeatures Description• Buffered Inputs The ’HC21 and CD74HCT21 logic gates utilize silicon gateCMOS ..
CD54HC21F3A ,High Speed CMOS Logic Dual 4-Input AND GatesCD54HC21, CD74HC21,CD74HCT21Data sheet acquired from Harris SemiconductorSCHS131CHigh-Speed CMOS Lo ..
CD54HC21F3A ,High Speed CMOS Logic Dual 4-Input AND GatesFeatures Description• Buffered Inputs The ’HC21 and CD74HCT21 logic gates utilize silicon gateCMOS ..
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CD54HC21F3A
High Speed CMOS Logic Dual 4-Input AND Gates
CD54HC21, CD74HC21, CD74HCT21 SCHS131C High-Speed CMOS Logic August 1997 - Revised September 2003 Dual 4-Input AND Gate Features Description • Buffered Inputs The ’HC21 and CD74HCT21 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to = 5V, • Typical Propagation Delay: 9ns at V [ /Title CC LSTTL gates with the low power consumption of standard o C = 15pF, T = 25 C L A (CD74H CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin • Fanout (Over Temperature Range) C21, compatible with the standard LS logic family. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74H - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CT21) Ordering Information o o • Wide Operating Temperature Range . . . -55 C to 125 C /Subject TEMP. RANGE (High • Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE Speed • Significant Power Reduction Compared to LSTTL CD54HC21F3A -55 to 125 14 Ld CERDIP CMOS Logic ICs Logic CD74HC21E -55 to 125 14 Ld PDIP • HC Types Dual 4- - 2V to 6V Operation CD74HC21M -55 to 125 14 Ld SOIC Input - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC21MT -55 to 125 14 Ld SOIC at V = 5V CC CD74HC21M96 -55 to 125 14 Ld SOIC • HCT Types - 4.5V to 5.5V Operation CD74HCT21E -55 to 125 14 Ld PDIP - Direct LSTTL Input Logic Compatibility, CD74HCT21M -55 to 125 14 Ld SOIC V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT21MT -55 to 125 14 Ld SOIC l OL OH CD74HCT21M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC21 (CERDIP) CD74HC21, CD74HCT21 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 2D NC 3 12 2C 1C 4 11 NC 1D 5 10 2B 1Y 6 9 2A GND 7 8 2Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
