CD54HC109F3A. ,High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and ResetLogic Diagram5(11)S6(10)2(14)SJJ Q QFF7(9)3(13)K Q QKCL CL R4(12)CP1(15)R16VCC8GND2CD54HC109, CD74H ..
CD54HC10F ,High Speed CMOS Logic Triple 3-Input NAND GatesCD54HC10, CD74HC10,CD54HCT10, CD74HCT10Data sheet acquired from Harris SemiconductorSCHS128CHigh-Sp ..
CD54HC10F ,High Speed CMOS Logic Triple 3-Input NAND GatesFeatures Description[ /Title• Buffered Inputs The ’HC10 and ’HCT10 logic gates utilize silicon gate ..
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CD54HC10F3A ,High Speed CMOS Logic Triple 3-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD54HC109F3A-CD54HC109F3A.
High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E Dual J-K Flip-Flop with Set and Reset March 1998 - Revised October 2003 Positive-Edge Trigger Features Description • Asynchronous Set and Reset The ’HC109 and ’HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition • Schmitt Trigger Clock Inputs [ /Title of Clock (1CP and 2CP). (CD74H = 54MHz at V = 5V, C = 15pF, • Typical f MAX CC L The flip-flop is set and reset by active-low S and R, o T = 25 C C109, A respectively. A low on both the set and reset inputs CD74H simultaneously will force both Q and Q outputs high. • Fanout (Over Temperature Range) However, both set and reset going high simultaneously CT109) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads results in an unpredictable output condition. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads /Subject o o (Dual J- Ordering Information • Wide Operating Temperature Range . . . -55 C to 125 C K Flip- • Balanced Propagation Delay and Transition Times TEMP. RANGE Flop o PART NUMBER ( C) PACKAGE • Significant Power Reduction Compared to LSTTL with Set Logic ICs CD54HC109F3A -55 to 125 16 Ld CERDIP and CD54HCT109F3A -55 to 125 16 Ld CERDIP • HC Types Reset - 2V to 6V Operation CD74HC109E -55 to 125 16 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC109M -55 to 125 16 Ld SOIC at V = 5V CC CD74HC109MT -55 to 125 16 Ld SOIC • HCT Types CD74HC109M96 -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation CD74HCT109E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT109M -55 to 125 16 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT109MT -55 to 125 16 Ld SOIC CD74HCT109M96 -55 to 125 16 Ld SOIC Pinout NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of CD54HC109, CD54HCT109 250. (CERDIP) CD74HC109, CD74HCT109 (PDIP, SOIC) TOP VIEW 1R 1 16 V CC 1J 2 15 2R 1K 3 14 2J 1CP 4 13 2K 1S 5 12 2CP 1Q 6 11 2S 1Q 7 10 2Q GND 8 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
