CD54ACT138F3A ,3-to-8-Line Decoder/Demultiplexer Invertingmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD54ACT138F3A. ,3-to-8-Line Decoder/Demultiplexer Invertingmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD54ACT151F3A ,8-Input Multiplexermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD54ACT161F3A ,Synchronous Presettable Binary Counters CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 200 ..
CD54ACT161F3A ,Synchronous Presettable Binary Counterslogic diagram of the D/T flip-flops.3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265CD54ACT161, CD74AC ..
CD54ACT164F3A ,8-Bit Serial-In/Parallel-Out Shift RegistersFeatures Description[ /Title• Buffered Inputs The ’AC164 and ’ACT164 are 8-bit serial-in/parallel-o ..
CH7013A-T , Digital PC to TV Encoder
CH7013B-D , Digital PC to TV Encoder
CH7013B-DF , Digital PC to TV Encoder
CH706F-40PT , SCHOTTKY BARRIER DIODE VOLTAGE 45 Volts CURRENT 0.03 Ampere
CH706F-40PT , SCHOTTKY BARRIER DIODE VOLTAGE 45 Volts CURRENT 0.03 Ampere
CH715FPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.03 Ampere
CD54ACT138F3A-CD54ACT138F3A.
3-to-8-Line Decoder/Demultiplexer Inverting
Systems Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe ’ACT138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing
applications that require very short propagation-delay times. In high-performance memory systems, these
decoders can be used to minimize the effects of system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are
less than the typical access time of the memory. This means that the effective system delay introduced by the
decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications (see Application
Information).
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
G2A
G2B
GND
