CD54AC109F3A ,Dual J-K Flip-Flop with Set and Reset CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS326 – JAN ..
CD54AC138F3A ,3-to-8-Line Decoder/Demultiplexer Inverting CD54AC138, CD74AC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS328A – JANUARY 2003 – REVISED FE ..
CD54AC138F3A ,3-to-8-Line Decoder/Demultiplexer Invertingmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD54AC138F3A ,3-to-8-Line Decoder/Demultiplexer Inverting
CD54AC161F3A ,Synchronous Presettable Binary Counters
CD54AC161F3A ,Synchronous Presettable Binary Counters
CH7013A-T , Digital PC to TV Encoder
CH7013B-D , Digital PC to TV Encoder
CH7013B-DF , Digital PC to TV Encoder
CH706F-40PT , SCHOTTKY BARRIER DIODE VOLTAGE 45 Volts CURRENT 0.03 Ampere
CH706F-40PT , SCHOTTKY BARRIER DIODE VOLTAGE 45 Volts CURRENT 0.03 Ampere
CH715FPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.03 Ampere
CD54AC109F3A
Dual J-K Flip-Flop with Set and Reset
Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering informationThe ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
1CLK
1PRE
GND
2CLK
2PRE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
