CD4723BCN ,Dual 4-Bit/ 8-Bit Addressable LatchFeaturestive high clear input (CL), a data input (D) and eight outputsYWide supply voltage range 3. ..
CD4724BCM ,Dual 8-Bit Addressable LatchElectrical Characteristics” provide con-Small Outline 500 mWditions for actual device operation.Lea ..
CD4724BCM ,Dual 8-Bit Addressable LatchFeaturesThe CD4724BC is an 8-bit addressable latch with three
CD4723BCN
Dual 4-Bit Addressable Latch
TL/F/6003
CD4723BM/CD4723BC
Dual
4-Bit
Addressable
Latch
CD4724BM/CD4724BC
8-Bit
Addressable
Latch
February 1988
CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latch
General Description
The CD4723Bisa dual 4-bit addressable latch with com-
mon control inputs, includingtwo address inputs (A0, A1), active lowenable input(E), andan active high clear input
(CL). Each latchhasa data input(D)andfour outputs (Q0–
Q3). The CD4724Bisan 8-bit addressable latch with three
address inputs (A0–A2),an activelow enable input(E),ac-
tive high clear input (CL),a data input(D)and eight outputs
(Q0–Q7).
Datais enteredintoa particularbitinthe latch whenthatis
addressedbythe address inputsandthe enable(E)islow.
Data entryis inhibited when enable(E)is high.
When clear (CL) andenable(E)are high,alloutputsarelow.
When clear (CL)is highand enable(E)is low,the channel
demultiplexing occurs.Thebitthatis addressedhasanac-
tive output which followsthe data input whileall unad-
dressedbitsare held low. When operatinginthe address-
able latch mode(EeCLe low), changing more thanone
bitofthe address could imposea transient wrong address.
Therefore,this should onlybe done whileinthe memory
mode(Ee high,CLe low).
Features Wide supply voltage range 3.0Vto 15V High noise immunity 0.45 VDD (typ.) Low power TTL fanoutof2 driving74L
compatibility or 1driving74LS Serialto parallel capability Storage register capability Random (addressable) data entry Active high demultiplexing capability Common active high clear
Connection Diagrams
CD4723B
Dual-In-Line Package
TL/F/6003–1
Top View
CD4724B
Dual-In-Line Package
TL/F/6003–2
Top View
Order Number CD4723Bor
CD4724B
Truth Table
Mode Selection CL Addressed Unaddressed ModeLatch Latch L Follows Data HoldsPrevious Data Addressable Latch L Hold Previous Data HoldsPrevious Data Memory H Follows Data Resetto‘‘0’’ Demultiplexer H Resetto‘0’’ Resetto‘‘0’’ Clear
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
