CD4541BM96 , CMOS PROGRAMMABLE TIMERFeatures10th, 13th, or 16th counter stage. The desired stage is chosen• Low Symmetrical Output Resi ..
CD4541BPWR , CMOS PROGRAMMABLE TIMERFeatures10th, 13th, or 16th counter stage. The desired stage is chosen• Low Symmetrical Output Resi ..
CD4543 , CMOS BCD-TO-SEVEN-SEGMENT LATCH/DECODER/DRIVER FOR LIQUID-CRYSTAL DISPLAYS
CD4543BE ,CMOS BCD-to-Seven-Segment Latch/Decoder/Driver for Liquid-Crystal DisplaysMAXIMUM RATINGS, Absolute-Maximum Values:DC SUPPLY-VOLTAGE RANGE, (VDD)Voltages referenced to VSS T ..
CD4543BM ,CMOS BCD-to-Seven-Segment Latch/Decoder/Driver for Liquid-Crystal DisplaysMAXIMUM RATINGS, Absolute-Maximum Values:DC SUPPLY-VOLTAGE RANGE, (VDD)Voltages referenced to VSS T ..
CD4543BM ,CMOS BCD-to-Seven-Segment Latch/Decoder/Driver for Liquid-Crystal DisplaysCD4543B TypesCMOS BCD-to-Seven-SegmentLatch/Decoder/DriverFor Liquid-Crystal Displays 0::erHigh-Vol ..
CH411DPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.5 Ampere
CH411DPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.5 Ampere
CH491DPT , SCHOTTKY BARRIER DIODE VOLTAGE 25 Volts CURRENT 1 Ampere
CH495DPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.4 Ampere
CH501S-40PT , SCHOTTKY BARRIER DIODE VOLTAGE 45 Volts CURRENT 0.1 Ampere
CH511H-30PT , SURFACE MOUNT SCHOTTKY BARRIER DIODE VOLTAGE 30 Volts CURRENT 1.0 Ampere
CD4541BE-CD4541BM-CD4541BM96-CD4541BPWR
CMOS PROGRAMMABLE TIMER HIGH VOLTAGE TYPES(20V RATING)
CD4541B CMOS Programmable Timer High Voltage Types (20V Rating) SCHS085E – Revised September 2003 The output from this timer is the Q or Q output from the 8th, Features 10th, 13th, or 16th counter stage. The desired stage is chosen • Low Symmetrical Output Resistance, Typically 100Ω using time-select inputs A and B (see Frequency Select Table). at V = 15V DD The output is available in either of two modes selectable via the [ /Title • Built-In Low-Power RC Oscillator MODE input, pin 10 (see Truth Table). When this MODE input is (CD45 • Oscillator Frequency Range . . . . . . . . . . DC to 100kHz a logic “1”, the output will be a continuous square wave having N 41B) a frequency equal to the oscillator frequency divided by 2 . • External Clock (Applied to Pin 3) can be Used Instead /Sub- With the MODE input set to logic “0” and after a MASTER of Oscillator N RESET is initiated, the output (assuming Q output has been ject Frequency Divider or as a Single- • Operates as 2 N-1 selected) changes from a low to a high state after 2 counts Transition Timer (CMO and remains in that state until another MASTER RESET pulse Q Select Provides Output Logic Level Flexibility •Q/ S Pro- is applied or the MODE input is set to a logic “1”. • AUTO or MASTER RESET Disables Oscillator During gram- Timing is initialized by setting the AUTO RESET input (pin 5) to Reset to Reduce Power Dissipation logic “0” and turning power on. If pin 5 is set to logic “1”, the mable • Operates With Very Slow Clock Rise and Fall Times AUTO RESET circuit is disabled and counting will not start until Timer after a positive MASTER RESET pulse is applied and returns • Capable of Driving Six Low Power TTL Loads, Three High to a low level. The AUTO RESET consumes an appreciable Low-Power Schottky Loads, or Six HTL Loads Over Volt- amount of power and should not be used if low-power operation the Rated Temperature Range is desired. For reliable automatic power-on reset, V should age DD • Symmetrical Output Characteristics be greater than 5V. Types • 100% Tested for Quiescent Current at 20V The RC oscillator, shown in Figure 2, oscillates with a (20V • 5V, 10V, and 15V Parametric Ratings frequency determined by the RC network and is calculated Rat- • Meets All Requirements of JEDEC Standard No. 13B, using: ing)) “Standard Specifications for Description of ‘B’ Series CMOS Devices” Where f is between 1kHz 1 /Autho ---------------------------------- - f = and 100kHz 2.3 R C TC TC r () and R≥Ω 10k and ≈ 2R S TC Description /Key- CD4541B programmable timer consists of a 16-stage binary words counter, an oscillator that is controlled by external R-C compo- Ordering Information (Har- nents (2 resistors and a capacitor), an automatic power-on TEMP. RANGE ris reset circuit, and output control logic. The counter increments o PART NUMBER ( C) PACKAGE on positive-edge clock transitions and can also be reset via the Semi- CD4541BF3A -55 to 125 14 Ld CERDIP MASTER RESET input. con- CD4541BE -55 to 125 14 Ld PDIP ductor, CD4541BM -55 to 125 14 Ld SOIC CD400 Pinout CD4541BMT -55 to 125 14 Ld SOIC 0, CD4541BM96 -55 to 125 14 Ld SOIC CD4541B metal CD4541BNSR -55 to 125 14 Ld SOP (CERDIP, PDIP, SOIC, SOP, TSSOP) gate, CD4541BPW -55 to 125 14 Ld TSSOP TOP VIEW CMOS CD4541BPWR -55 to 125 14 Ld TSSOP R 1 14 V TC DD NOTE: When ordering, use the entire part number. The suffixes 96 , pdip, and R denote tape and reel. The suffix T denotes a small-quantity C 2 13 B TC cerdip, reel of 250. R 3 12 A mil, S mili- NC 4 11 NC tary, AUTO RESET 5 10 MODE mil MASTER RESET 6 9 Q/Q SELECT 8 OUTPUT V 7 SS CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
