CD4541 ,Programmable TimerGeneral Description Oscillator may be bypassed if external clock is availableThe CD4541BC Programma ..
CD4541BCM ,Programmable TimerCD4541BC Programmable TimerOctober 1987Revised May 2002CD4541BCProgrammable Timer
CD4541BCM ,Programmable TimerCD4541BC Programmable TimerOctober 1987Revised May 2002CD4541BCProgrammable Timer
CD4541BCM ,Programmable TimerCD4541BC Programmable TimerOctober 1987Revised May 2002CD4541BCProgrammable Timer
CD4541BCMX ,Programmable TimerCD4541BC Programmable TimerOctober 1987Revised May 2002CD4541BCProgrammable Timer
CD4541BCN ,Programmable TimerCD4541BC Programmable TimerOctober 1987Revised May 2002CD4541BCProgrammable Timer
CH351H-30PT , SCHOTTKY BARRIER DIODE VOLTAGE 30 Volts CURRENT 0.2 Ampere
CH411DPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.5 Ampere
CH411DPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.5 Ampere
CH491DPT , SCHOTTKY BARRIER DIODE VOLTAGE 25 Volts CURRENT 1 Ampere
CH495DPT , SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.4 Ampere
CH501S-40PT , SCHOTTKY BARRIER DIODE VOLTAGE 45 Volts CURRENT 0.1 Ampere
CD4541
Programmable Timer
CD4541BC Programmable Timer October 1987 Revised March 1999 CD4541BC Programmable Timer � Oscillator frequency range ≈ DC to 100 kHz General Description � Oscillator may be bypassed if external clock is available The CD4541BC Programmable Timer is designed with a (apply external clock to pin 3) 16-stage binary counter, an integrated oscillator for use � Automatic reset initializes all counters when power turns with an external capacitor and two resistors, output control on logic, and a special power-on reset circuit. The special fea- tures of the power-on reset circuit are first, no additional � External master reset totally independent of automatic static power consumption and second, the part functions reset operation across the full voltage range (3V–15V) whether power-on n � Operates at 2 frequency divider or single transition reset is enabled or disabled. timer Timing and the counter are initialized by turning on power, � Q/Q select provides output logic level flexibility if the power-on reset is enabled. When the power is � Reset (auto or master) disables oscillator during reset- already on, an external reset pulse will also initialize the ting to provide no active power dissipation timing and counter. After either reset is accomplished, the � Clock conditioning circuit permits operation with very oscillator frequency is determined by the external RC net- work. The 16-stage counter divides the oscillator frequency slow clock rise and fall times by any of 4 digitally controlled division ratios. � Wide supply voltage range—3.0V to 15V � High noise immunity—0.45 V (typ.) DD Features � 5V–10V–15V parameter ratings 8 10 13 16 � Available division ratios 2 , 2 , 2 , or 2 � Symmetrical output characteristics � Increments on positive edge clock transitions � Maximum input leakage 1 μA at 15V over full tempera- ture range � Built-in low power RC oscillator (±2% accuracy over temperature range and ±10% supply and ±3% over pro- � High output drive (pin 8) min. one TTL load cessing @ < 10 kHz) Ordering Code: Order Number Package Number Package Description CD4541BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4541BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC N.C.—Not connected Top View © 1999 DS006001.prf
