CD4099BCN ,8-Bit Addressable LatchFeaturesThe CD4099BC is an 8-bit addressable latch with three
CD4099BCN
8-Bit Addressable Latch
CD4099BC 8-Bit Addressable Latch October 1987 Revised April 2002 CD4099BC 8-Bit Addressable Latch General Description Features The CD4099BC is an 8-bit addressable latch with threeWide supply voltage range: 3.0V to 15V address inputs (A0–A2), an active low enable input (E),High noise immunity: 0.45 V (typ.) DD active high clear input (CL), a data input (D), and eight out- Low power TTL: fan out of 2 driving 74L puts (Q0–Q7). compatibility: or 1 driving 74LS Data is entered into a particular bit in the latch when that bit Serial to parallel capability is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH.Storage register capability When clear (CL) and enable (E) are HIGH, all outputs areRandom (addressable) data entry LOW. When clear (CL) is HIGH and enable (E) is LOW, the Active high demultiplexing capability channel demultiplexing occurs. The bit that is addressed Common active high clear has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Ordering Code: Order Number Package Number Package Description CD4099BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Top View Truth Table Mode Selection E CL Addressed Unaddressed Mode Latch Latch L L Follows Data Holds Previous Data Addressable Latch H L Holds Previous Data Holds Previous Data Memory L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear © 2002 DS005984
