CD4094BCWM ,8-Bit Shift Register/Latch with 3-STATE OutputsCD4094BC 8-Bit Shift Register/Latch with 3-STATE OutputsOctober 1987Revised April 2002CD4094BC8-Bit ..
CD4094BCWM ,8-Bit Shift Register/Latch with 3-STATE OutputsCD4094BC 8-Bit Shift Register/Latch with 3-STATE OutputsOctober 1987Revised April 2002CD4094BC8-Bit ..
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CD4094BNSR ,CMOS 8-Stage Shift-and-Store Bus RegisterMAXIMUM RATINGS, Atraoluttr-Maxintum Values:DC SUPPLY-VOLTAGE RANGE, (VDD)Voltages referenced to VS ..
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CD4094BCN-CD4094BCWM
8-Bit Shift Register/Latch with 3-STATE Outputs
CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs October 1987 Revised April 2002 CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs General Description Features The CD4094BC consists of an 8-bit shift register and aWide supply voltage range: 3.0V to 18V 3-STATE 8-bit latch. Data is shifted serially through theHigh noise immunity: 0.45 V (typ.) DD shift register on the positive transition of the clock. The out- Low power TTL compatibility: put of the last stage (Q ) can be used to cascade several S Fan out of 2 driving 74L or 1 driving 74LS devices. Data on the Q output is transferred to a second S 3-STATE outputs output, Q′ , on the following negative clock edge. S The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH. Ordering Code: Order Number Package Number Package Description CD4094BCWM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide CD4094BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View Truth Table Clock Output Strobe Data Parallel Outputs Serial Outputs Enable Q1 Q Q Q′ N S Σ (Note 1) 0 X X Hi-Z Hi-Z Q7 No Change 0 X X Hi-Z Hi-Z No Change Q7 1 0 X No Change No Change Q7 No Change 11 0 0 Q −1 Q7 No Change N 11 1 1 Q −1 Q7 No Change N 1 1 1 No Change No Change No Change Q7 X = Don't Care = HIGH-to-LOW = LOW-to-HIGH Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q . S © 2002 DS005983
