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CD4070TIN/a50000avaiQuad 2-Input EXCLUSIVE-OR Gate
CD4070TI/ST/NXPN/a4500avaiQuad 2-Input EXCLUSIVE-OR Gate


CD4070 ,Quad 2-Input EXCLUSIVE-OR GateElectrical Characteristics (Note 3)- 40°C +25°C +85°CSymbol Parameter Conditions UnitsMin Max Min ..
CD4070 ,Quad 2-Input EXCLUSIVE-OR GateFeatureslow power consumption, and high noise margin, theCD4070BC provide basic functions used in t ..
CD4070BCM ,Quad 2-Input Exclusive-OR GateCD4070BC Quad 2-Input EXCLUSIVE-OR GateOctober 1987Revised April 2002CD4070BCQuad 2-Input EXCLUSIVE ..
CD4070BCM ,Quad 2-Input Exclusive-OR GateElectrical Characteristics” providesSmall Outline 500 mWconditions for actual device operation.Lead ..
CD4070BCN ,Quad 2-Input Exclusive-OR GateElectrical Characteristics’’ provides conditions for actual deviceoperation.eNote 2: V 0V unless ot ..
CD4070BCN ,Quad 2-Input Exclusive-OR GateElectrical Characteristics (Note 3)−55°C +25°C +125°CSymbol Parameter Conditions UnitsMin Max Min ..
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CD4070
Quad 2-Input EXCLUSIVE-OR Gate
CD4070BC Quad 2-Input EXCLUSIVE-OR Gate October 1987 Revised January 1999 CD4070BC Quad 2-Input EXCLUSIVE-OR Gate protected from damage due to static discharge by diode General Description clamps to V and V . DD SS The CD4070BC employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, Features low power consumption, and high noise margin, the CD4070BC provide basic functions used in the implemen- � Wide supply voltage range: 3.0V to 15V tation of digital integrated circuit systems. The N- and P- � High noise immunity: 0.45 V typ. DD channel enhancement mode transistors provide a symmet- � Low power TTL compatibility: rical circuit with output swing essentially equal to the supply Fan out of 2 driving 74L or 1 driving 74LS voltage. No DC power other than that caused by leakage � Pin compatible to CD4030A current is consumed during static condition. All inputs are Equivalent to MM74C86 and MC14070B Ordering Code: Order Number Package Number Package Description CD4070BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body CD4070BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs Outputs Pin Assignments for SOIC and DIP AB Y LLL LH H HL H HH L Top View © 1999 DS005976.prf
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