CD4069UBSJ , Inverter CircuitsElectrical Characteristics (Note 3)- 40°C +25°C +85°CSymbol Parameter Conditions UnitsMin Max Min T ..
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CD4069UBSJ
Inverter Circuits
CD4069UBC Inverter Circuits October 1987 Revised January 1999 CD4069UBC Inverter Circuits All inputs are protected from damage due to static dis- General Description charge by diode clamps to V and V . DD SS The CD4069UB consists of six inverter circuits and is man- ufactured using complementary MOS (CMOS) to achieve Features wide power supply operating range, low power consump- tion, high noise immunity, and symmetric controlled rise � Wide supply voltage range: 3.0V to 15V and fall times. � High noise immunity: 0.45 V typ. DD This device is intended for all general purpose inverter � Low power TTL compatibility: Fan out of 2 driving 74L applications where the special characteristics of the or 1 driving 74LS MM74C901, MM74C907, and CD4049A Hex Inverter/Buff- � Equivalent to MM74C04 ers are not required. In those applications requiring larger noise immunity the MM74C14 or MM74C914 Hex Schmitt Trigger is suggested. Ordering Code: Order Number Package Number Package Description CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code. Connection Diagram Schematic Diagram Pin Assignments for SOIC and DIP © 1999 DS005975.prf
