CD4042BM ,Quad Clocked D LatchElectrical Characteristics’’ provide conditions for actual deviceoperation.eNote 2: V 0V unless oth ..
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CD4042BM
Quad Clocked D Latch
TL/F/5966
CD4042BM/CD4042BC
Quad
Clocked
Latch
March 1988
CD4042BM/CD4042BC Quad ClockedD Latch
General Description
The CD4042BM/CD4042BC quad clocked ‘‘D’’ latchisa
monolithic complementary MOS (CMOS) integrated circuit
constructed withP- and N-channel enhancement mode
transistors. The outputsQandQ either latchor followthe
data input dependingonthe clock level whichis pro-
grammedbythe polarityinput. Forpolaritye0;the informa-
tion presentatthe data inputis transferredtoQ andQ
during0 clock level; andforpolaritye 1,the transfer occurs
duringthe1 clock level. Whena clock transition occurs
(positivefor polaritye0and negativefor polaritye1),the
information presentatthe input duringthe clock transitionis
retainedatthe outputs untilan opposite clock transitionoc-
curs.
Features Wide supply voltage range 3.0Vto 15V High noise immunity 0.45 VDD (typ.) Low power TTL Fanoutof2 driving 74L
compatibility or1 driving 74LS Clock polarity control Fully buffered data inputsQandQ outputs
Connection Diagram
Dual-In-Line Package
TL/F/5966–1
Top View
Truth Table
Clock Polarity Q D 0 Latch D 1 Latch
OrderNumberCD4042B
Logic Diagrams
TL/F/5966–2
TL/F/5966–3
TL/F/5966–4
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
