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CD4027BM
Dual J-K Master/Slave Flip-Flop with Set and Reset
TL/F/5958
CD4027BM/CD4027BC
Dual
J-K
Master/Slave
Flip-Flop
with
Set
and
Reset
February 1988
CD4027BM/CD4027BC Dual J-K Master/Slave
Flip-Flop with Set and Reset
General Description
These dual J-K flip-flopsare monolithic complementary
MOS (CMOS) integrated circuits constructed withN-andP-
channel enhancement mode transistors. Each flip-flophas
independentJ,K,set, reset,and clock inputsand bufferedandQ outputs. These flip-flopsare edge sensitivetothe
clockinputand change state onthe positive-going transitionthe clock pulses.Setor resetis independentofthe clock
andis accomplishedbya high levelonthe respective input.
All inputsare protected against damagedueto staticdis-
chargeby diode clampsto VDDand VSS.
Features Wide supply voltage range 3.0Vto 15V High noise immunity 0.45 VDD (typ.) Low power TTL Fanoutof2 driving 74L
compatibility or 1driving74LS Low power 50nW (typ.) Medium speed operation 12 MHz (typ.)
with10V supply
Schematic and Connection Diagrams
TL/F/5958–1
Dual-In-Line Package
TL/F/5958–2
Top View
OrderNumberCD4027B
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
