CD4027BCMX , Dual J-K Master/Slave Flip-Flop with Set and ResetCD4027BC Dual J-K Master/Slave Flip-Flop with Set and ResetOctober 1987Revised January 1999CD4027BC ..
CD4027BCMX , Dual J-K Master/Slave Flip-Flop with Set and ResetFeaturesN- and P-channel enhancement mode transistors. Eachflip-flop has independent J, K, set, res ..
CD4027BCN ,Dual J-K Master/Slave Flip-Flop with Set and ResetFeaturesThe CD4027BC dual J-K flip-flops are monolithic comple-
CD4027BCMX
Dual J-K Master/Slave Flip-Flop with Set and Reset
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset All inputs are protected against damage due to static dis- General Description charge by diode clamps to V and V . DD SS The CD4027BC dual J-K flip-flops are monolithic comple- mentary MOS (CMOS) integrated circuits constructed with Features N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs � Wide supply voltage range: 3.0V to 15V and buffered Q and Q outputs. These flip-flops are edge � High noise immunity: 0.45 V (typ.) DD sensitive to the clock input and change state on the posi- � Low power TTL compatibility: Fan out of 2 driving 74L tive-going transition of the clock pulses. Set or reset is or 1 driving 74LS independent of the clock and is accomplished by a high � Low power: 50 nW (typ.) level on the respective input. � Medium speed operation: 12 MHz (typ.) with 10V supply Ordering Code: Order Number Package Number Package Description CD4027BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4027BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs t Outputs t Pin Assignments for DIP and SOIC n−1 n (Note 1) (Note 2) CL JK S R Q Q Q (Note 3) I X OOO I O X OOO I I O O X OOO O I XI O O I O I X X O O X (No Change) XX X I O X I O XX X O I X O I XX X I I X I I I = HIGH Level O = LOW Level Top View X = Don't Care = LOW-to-HIGH = HIGH-to-LOW Note 1: t refers to the time interval prior to the positive clock pulse n−1 transition Note 2: t refers to the time intervals after the positive clock pulse n transition Note 3: Level Change © 1999 DS005958.prf
