CD4027BCM ,Dual J-K Master/Slave Flip-Flop with Set and ResetCD4027BC Dual J-K Master/Slave Flip-Flop with Set and ResetOctober 1987Revised January 2004CD4027BC ..
CD4027BCM ,Dual J-K Master/Slave Flip-Flop with Set and ResetFeaturesThe CD4027BC dual J-K flip-flops are monolithic comple-
CD4027BCM-CD4027BCN
Dual J-K Master/Slave Flip-Flop with Set and Reset
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 2004 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description Features The CD4027BC dual J-K flip-flops are monolithic comple-Wide supply voltage range: 3.0V to 15V mentary MOS (CMOS) integrated circuits constructed withHigh noise immunity: 0.45 V (typ.) DD N- and P-channel enhancement mode transistors. Each Low power TTL compatibility: Fan out of 2 driving 74L flip-flop has independent J, K, set, reset, and clock inputs or 1 driving 74LS and buffered Q and Q outputs. These flip-flops are edge Low power: 50 nW (typ.) sensitive to the clock input and change state on the posi- tive-going transition of the clock pulses. Set or reset isMedium speed operation: 12 MHz (typ.) with 10V independent of the clock and is accomplished by a high supply level on the respective input. All inputs are protected against damage due to static dis- charge by diode clamps to V and V . DD SS Ordering Code: Order Number Package Number Package Description CD4027BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4027BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table Inputs t Outputs t n−1 n (Note 1) (Note 2) CL JK S R Q Q Q (Note 3) I X OOO I O X OOO I I O O X OOO O I XI O O I O I X X O O X (No Change) XX X I O X I O XX X O I X O I XX X I I X I I I = HIGH Level O = LOW Level X = Don’t Care Top View = LOW-to-HIGH = HIGH-to-LOW Note 1: t refers to the time interval prior to the positive clock pulse n−1 transition Note 2: t refers to the time intervals after the positive clock pulse n transition Note 3: Level Change © 2004 DS005958
