CD4023BCMX ,Buffered Triple 3-Input NAND GateElectrical Characteristics (Note 4)−55°C +25°C +125°CSymbol Parameter Conditions UnitsMin Typ Min T ..
CD4023BCN ,Buffered Triple 3-Input NAND GateFeaturesThese triple gates are monolithic complementary MOS
CD4023BCM-CD4023BCMX-CD4023BCN
Buffered Triple 3-Input NAND Gate
CD4023BC Buffered Triple 3-Input NAND Gate October 1987 Revised January 2004 CD4023BC Buffered Triple 3-Input NAND Gate General Description Features These triple gates are monolithic complementary MOSWide supply voltage range: 3.0V to 15V (CMOS) integrated circuits constructed with N- and P-High noise immunity: 0.45 V (typ) DD channel enhancement mode transistors. They have equal Low power TTL compatibility: source and sink current capabilities and conform to stan- fan out of 2 driving 74L or 1 driving 74LS dard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing5V–10V–15V parametric ratings very high gain. All inputs are protected against static dis- Symmetrical output characteristics charge with diodes to V and V . DD SS Maximum input leakage 1 μA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4023BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) CD4023BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4023BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code. Connection Diagram Block Diagram 1 / Device Shown 3 *All Inputs Protected by Standard CMOS Input Protection Circuit. Top View © 2004 DS005956
