CD4021 ,8-Stage Static Shift RegisterElectrical Characteristics” providesLead Temperature (T )Lconditions for actual device operation.(S ..
CD4021 ,8-Stage Static Shift RegisterFeaturesual JAM inputs to each of 8 stages. Q outputs are availablefrom the sixth, seventh, and eig ..
CD4021B ,CMOS 8-Stage Static Shift RegisterFeatures:I Medium-speed operation . . . " MHz (tpr clockrate at VDD-USS = 10 VI Fully static operat ..
CD4021BCM ,8-Stage Static Shift RegisterFeaturesThe CD4021BC is an 8-stage parallel input/serial output
CD4021
8-Stage Static Shift Register
CD4021BC 8-Stage Static Shift Register October 1987 Revised January 1999 CD4021BC 8-Stage Static Shift Register All inputs are protected against static discharge with diodes General Description to V and V . DD SS The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individ- Features ual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have � Wide supply voltage range: 3.0V to 15V equal source and sink current capabilities and conform to � High noise immunity: 0.45 V (typ.) DD standard “B” series output drive. � Low power TTL compatibility: When the parallel/serial control input is in the logical “0” Fan out of 2 driving 74L or 1 driving 74LS state, data is serially shifted into the register synchronously � 5V–10V–15V parametric ratings with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into � Symmetrical output characteristics each stage of the register asynchronously with the clock. � Maximum input leakage 1 μA at 15V over full tempera- ture range Ordering Code: Order Number Order Code Package Description CD4021BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4021BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Parallel/ Pin Assignments for DIP and SOIC CL Serial Q1 Q n Serial PI 1 PI n (Note 1) Input (Internal) (Note 2) Control XX 1 0 0 0 0 XX 1 0 1 0 1 XX 1 1 0 1 0 XX 1 1 1 1 1 00 XX 0 Q n−1 10 XX 1 Q n−1 X0 XX Q1 Q n X = Don't care case Note 1: Level change Note 2: No change Top View © 1999 DS005954.prf
