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CD4019BCM-CD4019BCN
Quad AND-OR Select Gate
CD4019BC Quad AND-OR Select Gate October 1987 Revised January 1999 CD4019BC Quad AND-OR Select Gate General Description Features The CD4019BC is a complementary MOS quad AND-OR � Wide supply voltage range: 3.0V to 15V select gate. Low power and high noise margin over a wide � High noise immunity: 0.45 V (typ.) DD voltage range is possible through implementation of N- and � Low power TTL compatibility: Fan out of 2 driving 74L P-channel enhancement mode transistors. These comple- or 1 driving 74LS mentary MOS (CMOS) transistors provide the building blocks for the 4 “AND-OR select” gate configurations, each Applications consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits K and A • AND-OR select gating K . All inputs are protected against static discharge dam- B • Shift-right/shift-left registers age. • True/complement selection • AND/OR/EXCLUSIVE-OR selection Ordering Code: Order Number Package Number Package Description CD4019BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4019BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4019BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC and SOP Top View © 1999 DS005952.prf
