CD4015 ,Dual 4-Bit Static Shift RegisterApplications• Serial-input/parallel-output data queueing• Serial to parallel data conversion• Gener ..
CD4015BCM ,Dual 4-Bit Static Shift RegisterFeaturesThe CD4015BC contains two identical, 4-stage, serial-
CD4015
Dual 4-Bit Static Shift Register
CD4015BC Dual 4-Bit Static Shift Register October 1987 Revised January 1999 CD4015BC Dual 4-Bit Static Shift Register General Description Features The CD4015BC contains two identical, 4-stage, serial- � Wide supply voltage range: 3.0V to 18V input/parallel-output registers with independent “Data”, � High noise immunity: 0.45 V (typ.) DD “Clock,” and “Reset” inputs. The logic level present at the � Low power TTL: Fan out of 2 driving 74L input of each stage is transferred to the output of that stage compatibility: or 1 driving 74LS at each positive-going clock transition. A logic high on the “Reset” input resets all four stages covered by that input. � Medium speed operation: 8 MHz (typ.) clock rate All inputs are protected from static discharge by a series � Fully static design: @V − V = 10V DD SS resistor and diode clamps to V and V . DD SS Applications • Serial-input/parallel-output data queueing • Serial to parallel data conversion • General purpose register Ordering Code: Order Number Package Number Package Description CD4015BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4015BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP and SOIC CL DR Q Q 1 n (Note 1) 00 0 Q n−1 10 1 Q n−1 X0 Q Q (No change) 1 n XX 1 0 0 X = Don't Care Case Note 1: Level Change © 1999 DS005948.prf
