CD40147BE ,10-Line to 4-Line BCD Priority Encoderfeatures priorityencoding of the inputs to ensure that only thehighest-order data line is encoded. ..
CD4014BCN ,8-Stage Static Shift RegisterFeaturesual JAM inputs to each of 8 stages. Q outputs are availablefrom the sixth, seventh and eigh ..
CD4014BE ,CMOS 8-Stage Static Shift RegisterLogic diagram for 6040145.m _ P2” w:* 'dy v5” '2U 97* pa.'scam. , E gINPUYP p p p P p p P"uy-fyxrly ..
CD4014BF3A ,CMOS 8-Stage Static Shift RegisterFeatures:I Medium-speed operation . . . " MHz (tpr clockrate at VDD-USS = 10 VI Fully static operat ..
CD4015 ,Dual 4-Bit Static Shift RegisterApplications• Serial-input/parallel-output data queueing• Serial to parallel data conversion• Gener ..
CD4015BCM ,Dual 4-Bit Static Shift RegisterFeaturesThe CD4015BC contains two identical, 4-stage, serial-
CD40147BE
10-Line to 4-Line BCD Priority Encoder
SCHS102C − Revised October 2003
The CD40147B CMOS encoder features priority
encoding of the inputs to ensure that only the
highest-order data line is encoded. Ten data
input lines (0-9) are encoded to four-line
(8, 4, 2, 1) BCD. The highest priority line is line 9.
All four output lines are logic 1 (VSS) when all
input lines are logic 0. All inputs and outputs are
buffered, and each output can drive one TTL
low-power Schottky load. The CD40147B is
functionally similar to the TTL54/74147 if pin 15
is tied low.
The CD40147B types are supplied in 16-lead
dual-in-line plastic packages (E suffix), 16-lead
small-outline packages (M, M96, MT, and NSR
suffixes), and 16-lead thin shrink small-outline
packages (PW and PWR suffixes).
