CD4011BC ,Quad 2-Input NAND Buffered B Series GateFeaturesThe CD4001BC and CD4011BC quad gates are monolithic
CD4011BC
Quad 2-Input NAND Buffered B Series Gate
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate October 1987 Revised March 2002 CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description Features The CD4001BC and CD4011BC quad gates are monolithicLow power TTL: complementary MOS (CMOS) integrated circuits con- Fan out of 2 driving 74L compatibility: or 1 driving 74LS structed with N- and P-channel enhancement mode tran-5V–10V–15V parametric ratings sistors. They have equal source and sink current Symmetrical output characteristics capabilities and conform to standard B series output drive. Maximum input leakage 1 μA at 15V over full The devices also have buffered outputs which improve temperature range transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to V and V . DD SS Ordering Code: Order Number Package Number Package Description CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP Pin Assignments for DIP and SOIC CD4001BC CD4011BC Top View Top View © 2002 DS005939
