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CD4007CM ,Dual Complementary Pair Plus InverterElectrical CharacteristicsLimitsSymbol Parameter Conditions - 40°C +25°C +85°CUnitsMin Typ Max Min ..
CD4007CM ,Dual Complementary Pair Plus InverterGeneral Descriptionstrained to be between V - 0.3V and V + 0.3V at allSS DDThe CD4007C consists of ..
CD4007CM ,Dual Complementary Pair Plus InverterCD4007C Dual Complementary Pair Plus InverterOctober 1987Revised January 1999CD4007CDual Complement ..
CD4007CN ,Dual Complementary Pair Plus InverterFeaturesfrom static discharge by diode clamps to V and V .DD SS Wide supply voltage range: 3.0V to ..
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CD4007UBF ,CMOS Dual Complementary Pair Plus InverterFeatures:I Standardized symmetrical output characteristicsI Medium Speed Operation ‘tPH L. ‘PLH = 3 ..
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CD4007CM-CD4007CN
Dual Complementary Pair Plus Inverter
CD4007C Dual Complementary Pair Plus Inverter October 1987 Revised January 1999 CD4007C Dual Complementary Pair Plus Inverter For proper operation the voltages at all pins must be con- General Description strained to be between V − 0.3V and V + 0.3V at all SS DD The CD4007C consists of three complementary pairs of N- times. and P-channel enhancement mode MOS transistors suit- able for series/shunt applications. All inputs are protected Features from static discharge by diode clamps to V and V . DD SS � Wide supply voltage range: 3.0V to 15V � High noise immunity: 0.45 V (typ.) CC Ordering Code: Order Number Package Number Package Description CD4007CM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4007CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS–001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Note: All P-channel substrates are connected to V and all N-channel substrates are connected to V . DD SS Top View © 1999 DS005943.prf
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